Embedded/ EDA / VLSI/ASIC/ Chip Design Jobs- Walk in on 18th, 19th February 2012

Posted on February 16th, 2012

Team Lead/Technical Lead

Qualification: BE/B.Tech or ME/M.Tech/MS

Job Description:

ASIC VERIFICATION (Job Code: ASIC-V) Experience: 2 to 10 years’ experience in the following areas:

Multiple skills required:
Expertise in System Verilog & OVM /UVM / VMM .
Expertise in System Verilog & e-specman.
Expertise in Mixed Signal Verification.

Job Location: Hyderabad , Bangalore & Noida .

Logic Design: (Job Code: ASIC- LD) Experience: 2 to 7 years’ experience in the following areas: Microarchitecture, Logic Design, RTL Coding, Logic Synthesis, Expertise on ARM and Cortex processors and designing subsystems around them.

Job Location: Hyderabad , Bangalore & Noida.

ASIC Custom Layout (Job Code: ASIC- CL) Experience: 2 to 7 years’ experience in the following areas: Exposure to Calibre, Hercules and Assura, Strong basics in process technology, fabrication techniques
Strong expertise in standard cell layout design and characterization

Job Location: Bangalore & Noida.
ASIC PHYSICAL DESIGN (Job Code: ASIC- PD) Experience: 2 to 10 years’ experience in the following areas: Partitioning, IO ring preparation, Floor Planning, PG planning, Place and Route, Clock Tree Synthesis, Timing Closure, Static Timing Analysis, IR drop analysis, Physical verification, Signal Integrity, Low Power design.

Job Location: Hyderabad ,Bangalore, Vizag & Noida.
Position: Physical Design Managers Experience: 8 to 14 years’ experience in the following areas:
Job description: 8-10+ years of experience, should be able to manage a team of 10+ physical design engineers with expertise on Partitioning, IO ring preparation, Floorplanning, PG planning, Place and Route, Clock Tree Synthesis, Timing Closure, Static Timing Analysis, IR drop analysis, Physical verification, Signal Integrity, Low Power design.

Job Location: Hyderabad ,Bangalore & Vizag .
ASIC DFT (Job Code: ASIC-DFT) Experience: 2 to 10 years’ experience in the following areas:Basic logic design, Verilog RTL and verification back ground with exposure to STA utilizing industry standard tools.
-Must possess a strong knowledge of DFT including JTAG, Boundary scan, MBIST, LBIST, scan, on-chip scan compression, fault models, ATPG, and fault simulation and AC scan for at speed testing.
-Expertise in industry standard EDA tools for DFT such as DFTAdvisor, fastscan/TestKompress, TetraMax, LogicVision.
-Experience in Full-Chip DFT implementation of Scan, EDT/Adaptive Scan, JTAG, MBIST, Transition and Path delay ATPG.
-Experience in Gate Level Simulations, Synthesis, STA and Formal Verification. Understanding of ATE and test engineering. Post-Silicon debug.
-Experience in DFT with Logic Vision tools is mandatory.

Job Location: Hyderabad & Bangalore .

Company Name: Infotech Enterprises Ltd

Walk-in Date: 18^th , 19th Feb 2012

Time: 09:00am to 02:00pm

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